#include "../../3.Library/Include/general.h"


#ifndef WROS_REGISTER_H
#define WROS_REGISTER_H


typedef enum IRQn
{
	/******  Cortex-M4 Processor Exceptions Numbers ***************************************************************/
	Cortex_M4_NonMaskableInt_IRQn   = -14,       /*!< 2 Non Maskable Interrupt                                    */
	Cortex_M4_HardFault_IRQn        = -13,       /*!< 3 Cortex-M4 Hard Fault Interrupt                            */
	Cortex_M4_MemoryManagement_IRQn = -12,       /*!< 4 Cortex-M4 Memory Management Interrupt                     */
	Cortex_M4_BusFault_IRQn         = -11,       /*!< 5 Cortex-M4 Bus Fault Interrupt                             */
	Cortex_M4_UsageFault_IRQn       = -10,       /*!< 6 Cortex-M4 Usage Fault Interrupt                           */
	Cortex_M4_SVCall_IRQn           = -5,        /*!< 11 Cortex-M4 SV Call Interrupt                              */
	Cortex_M4_DebugMonitor_IRQn     = -4,        /*!< 12 Cortex-M4 Debug Monitor Interrupt                        */
	Cortex_M4_PendSV_IRQn           = -2,        /*!< 14 Cortex-M4 Pend SV Interrupt                              */
	Cortex_M4_SysTick_IRQn          = -1,        /*!< 15 Cortex-M4 System Tick Interrupt                          */

	/******  TMPM470 Specific Interrupt Numbers *******************************************************************/
	ExternalInterrupts_0			= 0,
	ExternalInterrupts_1			= 1,
	ExternalInterrupts_2			= 2,
	ExternalInterrupts_3			= 3,
	ExternalInterrupts_4			= 4,
	ExternalInterrupts_5			= 5,
	ExternalInterrupts_6			= 6,
	ExternalInterrupts_7			= 7,
	ExternalInterrupts_8			= 8,
	ExternalInterrupts_9			= 9,
	ExternalInterrupts_10			= 10,
	ExternalInterrupts_11			= 11,
	ExternalInterrupts_12			= 12,
	ExternalInterrupts_13			= 13,
	ExternalInterrupts_14			= 14,
	ExternalInterrupts_15			= 15,
	ExternalInterrupts_16			= 16,
	ExternalInterrupts_17			= 17,
	ExternalInterrupts_18			= 18,
	ExternalInterrupts_19			= 19,
	ExternalInterrupts_20			= 20,
	ExternalInterrupts_21			= 21,
	ExternalInterrupts_22			= 22,
	ExternalInterrupts_23			= 23,
	ExternalInterrupts_24			= 24,
	ExternalInterrupts_25			= 25,
	ExternalInterrupts_26			= 26,
	ExternalInterrupts_27			= 27,
	ExternalInterrupts_28			= 28,
	ExternalInterrupts_29			= 29,
	ExternalInterrupts_30			= 30,
	ExternalInterrupts_31			= 31,
	ExternalInterrupts_32			= 32,
	ExternalInterrupts_33			= 33,
	ExternalInterrupts_34			= 34,
	ExternalInterrupts_35			= 35,
	ExternalInterrupts_36			= 36,
	ExternalInterrupts_37			= 37,
	ExternalInterrupts_38			= 38,
	ExternalInterrupts_39			= 39,
	ExternalInterrupts_40			= 40,
	ExternalInterrupts_41			= 41,
	ExternalInterrupts_42			= 42,
	ExternalInterrupts_43			= 43,
	ExternalInterrupts_44			= 44,
	ExternalInterrupts_45			= 45,
	ExternalInterrupts_46			= 46,
	ExternalInterrupts_47			= 47,
	ExternalInterrupts_48			= 48,
	ExternalInterrupts_49			= 49,
	ExternalInterrupts_50			= 50,
	ExternalInterrupts_51			= 51,
	ExternalInterrupts_52			= 52,
	ExternalInterrupts_53			= 53,
	ExternalInterrupts_54			= 54,
	ExternalInterrupts_55			= 55,
	ExternalInterrupts_56			= 56,
	ExternalInterrupts_57			= 57,
	ExternalInterrupts_58			= 58,
	ExternalInterrupts_59			= 59,
	ExternalInterrupts_60			= 60,
	ExternalInterrupts_61			= 61,
	ExternalInterrupts_62			= 62,
	ExternalInterrupts_63			= 63,
	ExternalInterrupts_64			= 64,
	ExternalInterrupts_65			= 65,
	ExternalInterrupts_66			= 66,
	ExternalInterrupts_67			= 67,
	ExternalInterrupts_68			= 68,
	ExternalInterrupts_69			= 69,
	ExternalInterrupts_70			= 70,
	ExternalInterrupts_71			= 71,
	ExternalInterrupts_72			= 72,
	ExternalInterrupts_73			= 73,
	ExternalInterrupts_74			= 74,
	ExternalInterrupts_75			= 75,
	ExternalInterrupts_76			= 76,
	ExternalInterrupts_77			= 77,
	ExternalInterrupts_78			= 78,
	ExternalInterrupts_79			= 79,
	ExternalInterrupts_80			= 80,
	ExternalInterrupts_81			= 81,
	ExternalInterrupts_82			= 82,
	ExternalInterrupts_83			= 83,
	ExternalInterrupts_84			= 84,
	ExternalInterrupts_85			= 85,
	ExternalInterrupts_86			= 86,
	ExternalInterrupts_87			= 87,
	ExternalInterrupts_88			= 88,
	ExternalInterrupts_89			= 89,
	ExternalInterrupts_90			= 90,
} WROS_IRQn_Type;

#if defined(TMPM470) || defined(TMPM380)

typedef struct {
	uint32_t RESERVED;					// 0xE000E000
	uint32_t ICTR;						// 0xE000E004: (R/ ) Interrupt Controller Type Register, ICTR

	union {
		volatile uint32_t ACTLR;			// 0xE000E008: (R/W) Auxiliary Control Register, ACTLR on page 4-5
		struct ACTLR_Register {
			uint32_t DISMCYCINT	: 1;		
			uint32_t DISDEFWBUF	: 1;		
			uint32_t DISFOLD		: 1;	// Disables folding of IT instructions.
			uint32_t RESERVED0	: 5;
			uint32_t DISOOFP		: 1;	// Disables floating point instructions completing out of order with respect to integer instructions.
			uint32_t DISFPCA		: 1;	// Disables lazy stacking of floating point context. See Exceptions on page 7-8 for more information.
		} ACTLR_register;
	};
	
	struct SYSTICK_Register {
		uint32_t RESERVED0;				// 0xE000E00C:
		uint32_t STCSR;					// 0xE000E010: (R/W) SysTick Control and Status Register
		uint32_t STRVR;					// 0xE000E014: (R/W) SysTick Reload Value Register
		uint32_t STCVR;					// 0xE000E018: (R/W) SysTick Current Value Register
		uint32_t STCR;	//	STCALIB		// 0xE000E01C: (R/ ) SysTick Calibration Value Register
		uint32_t RESERVED1[56];			// 0xE000E020: ( / ) SysTick Current Value Register
	} SYSTICK_register;
	
	struct NVIC_Register {

		uint32_t ISER[8];					// 0xE000E100: (R/W) Interrupt Set Enable Register
		uint32_t RESERVED2[24];							
		uint32_t ICER[8];					// 0xE000E180: (R/W) Interrupt Clear Enable Register
		uint32_t RESERVED3[24]; 							
		uint32_t ISPR[8];					// 0xE000E200: (R/W) Interrupt Set Pending Register
		uint32_t RESERVED4[24];							
		uint32_t ICPR[8];					// 0xE000E280: (R/W) Interrupt Clear Pending Register
		uint32_t RESERVED5[24];							
		uint32_t IABR[8];					// 0xE000E300: (R/W) Interrupt Active bit Register
		uint32_t RESERVED6[56];
		uint8_t IPR[240];					// 0xE000E400: (R/W) Interrupt Active bit Register
		uint32_t RESERVED7[516];			// 0xE000E4F0
		
		union {
			volatile uint32_t CPUID;		// 0xE000ED00: (R/ ) CPU ID Base Register	// Reset 0x410FC240	
			struct CPUID_Register {
				uint32_t REVISION		: 4;		// Indicates patch release: 0x0 = Patch 0.
				uint32_t PARTNO		: 12;		// Indicates part number: 0xC24 = Cortex-M4
				uint32_t Constant		: 4;		// Reads as 0xF
				uint32_t VARIANT		: 4;		// Indicates processor revision: 0x0 = Revision 0
				uint32_t IMPLEMENTER	: 8;		// Indicates implementor: 0x41 = ARM
			} CPUID_register;
		};
		
		uint32_t ICSR;					// 0xE000ED04: (R/W)  Interrupt Control State Register
		uint32_t VTOR;					// 0xE000ED08: (R/W)  Vector Table Offset Register


		union {
			uint32_t AIRCR;					// 0xE000ED0C: (R/W)  Application Interrupt / Reset Control Register
			struct AIRCR_Register {
				uint32_t VECTRESET	: 1;		// Request CORTEX_M reset
				uint32_t VECTCLRACTIVE: 1;		// Clear all abnormal Info
				uint32_t SYSRESETREQ	: 1;		// Request MCU reset
				uint32_t RESERVED0	: 5;
				uint32_t PRIGROUP		: 3;		// Priority grouping
				uint32_t RESERVED1	: 4;
				uint32_t ENDIANESS	: 1;		// READ ONLY		1 = MSB, 0 = LSB
				uint32_t VECTKEY		: 16;		// OPER Key			WRITE: 0x05FA, READ: 0xFA05
			} AIRCR_register;
		};
		
		uint32_t SCR;						// 0xE000ED10: (R/W)  System Control Register							   
		uint32_t CCR;						// 0xE000ED14: (R/W)  Configuration Control Register 					   
		uint8_t  SHP[12];					// 0xE000ED18: (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) 
		uint32_t SHCSR;					// 0xE000ED24: (R/W)  System Handler Control and State Register			 
		uint32_t CFSR;					// 0xE000ED28: (R/W)  Configurable Fault Status Register 				   
		uint32_t HFSR;					// 0xE000ED2C: (R/W)  Hard Fault Status Register 						   
		uint32_t DFSR;					// 0xE000ED30: (R/W)  Debug Fault Status Register						   
		uint32_t MMFAR;					// 0xE000ED34: (R/W)  Mem Manage Address Register						   
		uint32_t BFAR;					// 0xE000ED38: (R/W)  Bus Fault Address Register 						   
		uint32_t AFSR;					// 0xE000ED3C: (R/W)  Auxiliary Fault Status Register					   
		uint32_t PFR[2];					// 0xE000ED40: (R/ )  Processor Feature Register 						   
		uint32_t DFR;						// 0xE000ED48: (R/ )  Debug Feature Register 							   
		uint32_t ADR;						// 0xE000ED4C: (R/ )  Auxiliary Feature Register 						   
		uint32_t MMFR[4];					// 0xE000ED50: (R/ )  Memory Model Feature Register						
		uint32_t ISAR[5];					// 0xE000ED60: (R/ )  ISA Feature Register								   
		uint32_t RESERVED8[5];
		uint32_t CPACR;					// 0xE000ED88: (R/W)  Coprocessor access register
		uint32_t RESERVED9;				// 0xE000ED8C
		uint32_t MPU_TYPE;				// 0xE000ED90: (R/ )  MPU Type Register
		uint32_t MPU_CTRL;				// 0xE000ED94: (R/W)  MPU Control Register
		uint32_t MPU_RNR;					// 0xE000ED98: (R/W)  MPU Region Number Register
		uint32_t MPU_RBAR;				// 0xE000ED9C: (R/W)  MPU Region Number Register
		uint32_t MPU_RASR;				// 0xE000EDA0: (R/W)  MPU Region Number Register
		uint32_t MPU_RBAR_A1;				// 0xE000EDA4: (R/W)  MPU alias registers
		uint32_t MPU_RASR_A1;				// 0xE000EDA8: (R/W)  
		uint32_t MPU_RBAR_A2;				// 0xE000EDAC: (R/W)  
		uint32_t MPU_RASR_A2;				// 0xE000EDB0: (R/W)  
		uint32_t MPU_RBAR_A3;				// 0xE000EDB4: (R/W)  
		uint32_t MPU_RASR_A3;				// 0xE000EDB8: (R/W)  
		uint32_t RESERVED10[81];			// 0xE000EDBC
		
		uint32_t STIR;					// 0xE000EF00: ( /W)  Software Triggered Interrupt Register
	}NVIC_register;
} WROS_CORE_M4_Typedef;


// Clock generator
typedef struct
{
	union {
		volatile	uint32_t SYSCR;         // System Control Register
		struct SYSCR_Register 
		{
            uint32_t GEAR 			: 3;        // 珂爐넷쫴롸틉궐：000=fc, 100=fc/2 된
            uint32_t Reserved_0		: 5;   		// 貫3-5，怜뗍0
            uint32_t PRCK 			: 3;        // 渡롸틉珂爐(┵T0)롸틉궐：000=fc, 001=fc/2 된
            uint32_t Reserved_1		: 1;   		// 貫3-5，怜뗍0
            uint32_t FPSSEL 		: 1;      	// 棍珂爐(fperiph)都朞嶝：0=fgear, 1=fc
            uint32_t Reserved_2		: 3;   		// 貫3-5，怜뗍0
            uint32_t Reserved_3		: 16;  		// 貫13-31，怜뗍0（貫17-16矜畇01?
		} SYSCR_register;
	};

	union {
		volatile	uint32_t OSCCR;         // Oscillation Control Register
		struct OSCCR_Register 
		{
            uint32_t WUEON			: 1;      	// 渡훑땍珂포왠齡：1=폘땡（畇0轟雷屢）
            uint32_t WUEF			: 1;       	// 渡훑땍珂포榴檄：0=供냥, 1=頓契
            uint32_t PLLON			: 1;      	// PLL꾸鱗왠齡：0=界岺, 1=驪뎬
            uint32_t WUPSEL1		: 1;    	// 渡훑땍珂포珂爐都，극伎畇0
            uint32_t Reserved_1		: 4;   		// 貫4-6，怜뗍0
            uint32_t XEN1			: 1;       	// 棍꼬멕醵驪뎬포(EOSC)賈콘：0=쐐痰, 1=賈콘
            uint32_t Reserved_2		: 7;   		// 貫9-15，畇0샀怜뗍0
            uint32_t XEN2			: 1;       	// 코꼬멕醵驪뎬포(IOSC)賈콘：0=쐐痰, 1=賈콘
            uint32_t OSCSEL			: 1;     	// 멕醵驪뎬포都朞嶝：0=코꼬(fiosc), 1=棍꼬(fosc)
            uint32_t Reserved_3		: 1;   		// 貫18，괏즛
            uint32_t WUPSEL2		: 1;    	// 渡훑땍珂포珂爐都朞嶝：0=코꼬(fiosc), 1=棍꼬(fosc)
            uint32_t WUODR			: 12;   	// 멕醵驪뎬포渡훑땍珂포궐싹令（12貫）
		} OSCCR_register;
	};


	union {
		volatile	uint32_t STBYCR;            // Standby Control Register
		struct STBYCR_Register
		{
            uint32_t STBY			: 3;       	// 됴묘봬친駕朞嶝：001=STOP, 011=IDLE 된
            uint32_t Reserved_0		: 5; 		// 貫3-7，怜뗍0
            uint32_t RXEN			: 1;       	// STOP친駕藁놔빈멕醵驪뎬포賈콘，畇1
            uint32_t Reserved_1		: 7;   		// 貫9-15，畇0샀怜뗍0
            uint32_t Reserved_2		: 16;  		// 貫16-31，怜뗍0샀畇0
		} STBYCR_register;
	};

	union {
		volatile	uint32_t PLLSEL;            // PLL Selection Register
		struct PLLSEL_Register 
		{
            uint32_t PLLSEL			: 1;     	// 멕醵珂爐(fc)都朞嶝：0=fosc, 1=fpu
            uint32_t PLLSET			: 15;   	// PLL굡藤令（흔0x591E뚤壇10MHz渴흙∪80MHz渴놔된）
            uint32_t Reserved_0		: 16;  		// 貫16-31，怜뗍0
		} PLLSEL_register;
	};

	uint32_t RESERVED0;

	union {
		volatile	uint32_t ICRCG;             // CG Interrupt Request Clear Register
		struct ICRCG_Register {
			uint32_t ICRCG			: 5;		
            uint32_t Reserved_0		: 3;
            uint32_t Reserved_1		: 24;  		// 貫16-31，怜뗍0
		} ICRCG_register;
	};

	uint32_t RESERVED1;

	union {
		volatile	uint32_t RSTFLG;            // Reset Flag Register
		struct RSTFLG_Register {
            uint32_t PONRSTF		: 1;    	// 든릿貫깃羚：bit0，뗍1깊刻든릿貫，畇0헌뇜
            uint32_t PINRSTF		: 1;    	// 릿貫多신깃羚：bit1，뗍1깊刻릿貫多신뇰랙，畇0헌뇜
            uint32_t WDTRSTF		: 1;    	// 였쳔뭍릿貫깃羚：bit2，뗍1깊刻WDT뇰랙，畇0헌뇜
            uint32_t VLTDRSTF		: 1;   		// 든箕쇱꿎릿貫깃羚：bit3，뗍1깊刻VLTD뇰랙，畇0헌뇜
            uint32_t DBGRSTF		: 1;   		// 딧桿릿貫깃羚：bit4，뗍1깊刻SYSRESETREQ뇰랙，畇0헌뇜
            uint32_t OFDRSTF		: 1;   		// OFD릿貫깃羚：bit5，뗍1깊刻OFD뇰랙，畇0헌뇜
            uint32_t Reserved_0	: 2; 		// bit6-7，怜뗍0
            uint32_t Reserved_1	: 24;		// bit8-31，怜뗍0
		} RSTFLG_register;
	};

	union {
		volatile	uint32_t IMCGA;             // CG Interrupt Mode Control Register A
		struct IMCGA_Register {
            uint32_t INT00EN		: 1;    	// INT00賈콘：bit0，0=쐐痰，1=賈콘
            uint32_t Reserved_0 	: 1; 		// bit1，undefined
            uint32_t EMST00		: 2;     	// INT00긋懶왠齡：bit3-2
            uint32_t EMCG00		: 3;     	// INT00친駕왠齡：bit7-6
            uint32_t Reserved_1 	: 1; 		// bit1，undefined
			
            uint32_t INT01EN		: 1;    	// INT01賈콘：bit8，0=쐐痰，1=賈콘
            uint32_t Reserved_2 	: 1; 		// bit9，undefined
            uint32_t EMST01		: 2;     	// INT01긋懶왠齡：bit11-10
            uint32_t EMCG01		: 3;     	// INT01친駕왠齡：bit15-14
            uint32_t Reserved_3 	: 1; 		// bit9，undefined
			
            uint32_t INT02EN		: 1;    	// INT02賈콘：bit16，0=쐐痰，1=賈콘
            uint32_t Reserved_4 	: 1; 		// bit17，undefined
            uint32_t EMST02		: 2;     	// INT02긋懶왠齡：bit19-18
            uint32_t EMCG02		: 3;     	// INT02친駕왠齡：bit23-22
            uint32_t Reserved_5 	: 1; 		// bit9，undefined
			
            uint32_t INT03EN		: 1;   		// INT03賈콘：bit24，0=쐐痰，1=賈콘
            uint32_t Reserved_6 	: 1; 		// bit25，undefined
            uint32_t EMST03		: 2;     	// INT03긋懶왠齡：bit27-26
            uint32_t EMCG03		: 3;     	// INT03친駕왠齡：bit31-30
            uint32_t Reserved_7 	: 1; 		// bit9，undefined
		} IMCGA_register;
	};
	
	union {
		volatile	uint32_t IMCGB;             // CG Interrupt Mode Control Register B
		struct IMCGB_Register {
            uint32_t INT04EN		: 1;    	// INT00賈콘：bit0，0=쐐痰，1=賈콘
            uint32_t Reserved_0 	: 1; 		// bit1，undefined
            uint32_t EMST04		: 2;     	// INT00긋懶왠齡：bit3-2
            uint32_t EMCG04		: 3;     	// INT00친駕왠齡：bit7-6
            uint32_t Reserved_1 	: 1; 		// bit1，undefined
			
            uint32_t INT05EN		: 1;    	// INT01賈콘：bit8，0=쐐痰，1=賈콘
            uint32_t Reserved_2 	: 1; 		// bit9，undefined
            uint32_t EMST05		: 2;     	// INT01긋懶왠齡：bit11-10
            uint32_t EMCG05		: 3;     	// INT01친駕왠齡：bit15-14
            uint32_t Reserved_3 	: 1; 		// bit9，undefined
			
            uint32_t INT06EN		: 1;    	// INT02賈콘：bit16，0=쐐痰，1=賈콘
            uint32_t Reserved_4 	: 1; 		// bit17，undefined
            uint32_t EMST06		: 2;     	// INT02긋懶왠齡：bit19-18
            uint32_t EMCG06		: 3;     	// INT02친駕왠齡：bit23-22
            uint32_t Reserved_5 	: 1; 		// bit9，undefined
			
            uint32_t INT07EN		: 1;   		// INT03賈콘：bit24，0=쐐痰，1=賈콘
            uint32_t Reserved_6 	: 1; 		// bit25，undefined
            uint32_t EMST07		: 2;     	// INT03긋懶왠齡：bit27-26
            uint32_t EMCG07		: 3;     	// INT03친駕왠齡：bit31-30
            uint32_t Reserved_7 	: 1; 		// bit9，undefined
		} IMCGB_register;
	};
	
	union {
		volatile	uint32_t IMCGC;             // CG Interrupt Mode Control Register C
		struct IMCGC_Register {
            uint32_t INT08EN		: 1;    	// INT00賈콘：bit0，0=쐐痰，1=賈콘
            uint32_t Reserved_0 	: 1; 		// bit1，undefined
            uint32_t EMST08		: 2;     	// INT00긋懶왠齡：bit3-2
            uint32_t EMCG08		: 3;     	// INT00친駕왠齡：bit7-6
            uint32_t Reserved_1 	: 1; 		// bit1，undefined
			
            uint32_t INT09EN		: 1;    	// INT01賈콘：bit8，0=쐐痰，1=賈콘
            uint32_t Reserved_2 	: 1; 		// bit9，undefined
            uint32_t EMST09		: 2;     	// INT01긋懶왠齡：bit11-10
            uint32_t EMCG09		: 3;     	// INT01친駕왠齡：bit15-14
            uint32_t Reserved_3 	: 1; 		// bit9，undefined
			
            uint32_t INT0AEN		: 1;    	// INT02賈콘：bit16，0=쐐痰，1=賈콘
            uint32_t Reserved_4 	: 1; 		// bit17，undefined
            uint32_t EMST0A		: 2;     	// INT02긋懶왠齡：bit19-18
            uint32_t EMCG0A		: 3;     	// INT02친駕왠齡：bit23-22
            uint32_t Reserved_5 	: 1; 		// bit9，undefined
			
            uint32_t INT0BEN		: 1;   		// INT03賈콘：bit24，0=쐐痰，1=賈콘
            uint32_t Reserved_6 	: 1; 		// bit25，undefined
            uint32_t EMST0B		: 2;     	// INT03긋懶왠齡：bit27-26
            uint32_t EMCG0B		: 3;     	// INT03친駕왠齡：bit31-30
            uint32_t Reserved_7 	: 1; 		// bit9，undefined
		} IMCGC_register;
	};
	
	union {
		volatile	uint32_t IMCGD;             // CG Interrupt Mode Control Register D
		struct IMCGD_Register {
            uint32_t INT0CEN		: 1;    	// INT00賈콘：bit0，0=쐐痰，1=賈콘
            uint32_t Reserved_0 	: 1; 		// bit1，undefined
            uint32_t EMST0C		: 2;     	// INT00긋懶왠齡：bit3-2
            uint32_t EMCG0C		: 3;     	// INT00친駕왠齡：bit7-6
            uint32_t Reserved_1 	: 1; 		// bit1，undefined
			
            uint32_t INT0DEN		: 1;    	// INT01賈콘：bit8，0=쐐痰，1=賈콘
            uint32_t Reserved_2 	: 1; 		// bit9，undefined
            uint32_t EMST0D		: 2;     	// INT01긋懶왠齡：bit11-10
            uint32_t EMCG0D		: 3;     	// INT01친駕왠齡：bit15-14
            uint32_t Reserved_3 	: 1; 		// bit9，undefined
			
            uint32_t INT0EEN		: 1;    	// INT02賈콘：bit16，0=쐐痰，1=賈콘
            uint32_t Reserved_4 	: 1; 		// bit17，undefined
            uint32_t EMST0E		: 2;     	// INT02긋懶왠齡：bit19-18
            uint32_t EMCG0E		: 3;     	// INT02친駕왠齡：bit23-22
            uint32_t Reserved_5 	: 1; 		// bit9，undefined
			
            uint32_t INT0FEN		: 1;   		// INT03賈콘：bit24，0=쐐痰，1=賈콘
            uint32_t Reserved_6 	: 1; 		// bit25，undefined
            uint32_t EMST0F		: 2;     	// INT03긋懶왠齡：bit27-26
            uint32_t EMCG0F		: 3;     	// INT03친駕왠齡：bit31-30
            uint32_t Reserved_7 	: 1; 		// bit9，undefined
		} IMCGD_register;
	};

} WROS_CLKGE_TypeDef;





typedef struct
{
	// MOD (WD Mode Register)
    union {
        volatile uint32_t WDT_MOD;                // WD Mode Register
        struct WDT_MOD_Register {
            uint32_t RESERVED_0	: 1;		// Write 0
            uint32_t RESCR		: 1;
            uint32_t I2WDT		: 1; 
            uint32_t RESERVED_1	: 1; 
            uint32_t WDTP		: 3; 
            uint32_t WDTE		: 1; 
            uint32_t RESERVED_2	: 24; 
        } WDT_MOD_register;
    };
	
	// CR (WD Control Register)
    union {
        volatile uint32_t WDT_CR;                // WD Control Register
        struct WDT_CR_Register {
            uint32_t TMCR		: 8;
            uint32_t RESERVED_0	: 24; 
        } WDT_CR_register;
    };
} WROS_WDT___TypeDef;

typedef struct {
    // 鑒앴셍닸포：16몸多신데뗌왠齡
	union {
		volatile uint32_t DATA;              /*!< Port Data Register                           */
		struct DATA_Register {
			uint32_t DATA_0      : 1;    /*!< Pin 0 Data (0: Low, 1: High)                 */
			uint32_t DATA_1      : 1;    /*!< Pin 1 Data (0: Low, 1: High)                 */
			uint32_t DATA_2      : 1;    /*!< Pin 2 Data (0: Low, 1: High)                 */
			uint32_t DATA_3      : 1;    /*!< Pin 3 Data (0: Low, 1: High)                 */
			uint32_t DATA_4      : 1;    /*!< Pin 4 Data (0: Low, 1: High)                 */
			uint32_t DATA_5      : 1;    /*!< Pin 5 Data (0: Low, 1: High)                 */
			uint32_t DATA_6      : 1;    /*!< Pin 6 Data (0: Low, 1: High)                 */
			uint32_t DATA_7      : 1;    /*!< Pin 7 Data (0: Low, 1: High)                 */
			uint32_t DATA_8      : 1;    /*!< Pin 8 Data (0: Low, 1: High)                 */
			uint32_t DATA_9      : 1;    /*!< Pin 9 Data (0: Low, 1: High)                 */
			uint32_t DATA_10     : 1;    /*!< Pin 10 Data (0: Low, 1: High)                */
			uint32_t DATA_11     : 1;    /*!< Pin 11 Data (0: Low, 1: High)                */
			uint32_t DATA_12     : 1;    /*!< Pin 12 Data (0: Low, 1: High)                */
			uint32_t DATA_13     : 1;    /*!< Pin 13 Data (0: Low, 1: High)                */
			uint32_t DATA_14     : 1;    /*!< Pin 14 Data (0: Low, 1: High)                */
			uint32_t DATA_15     : 1;    /*!< Pin 15 Data (0: Low, 1: High)                */
			uint32_t RESERVED    : 16;   /*!< Reserved Bits                                */
		} DATA_register;
	};

    // 渴놔왠齡셍닸포：16몸多신데뗌賈콘
    union {
        volatile uint32_t CR;                /*!< Port Output Control Register                 */
        struct CR___Register {
            uint32_t CR___0        : 1;    /*!< Pin 0 Output Enable (0: Disable, 1: Enable)  */
            uint32_t CR___1        : 1;    /*!< Pin 1 Output Enable (0: Disable, 1: Enable)  */
            uint32_t CR___2        : 1;    /*!< Pin 2 Output Enable (0: Disable, 1: Enable)  */
            uint32_t CR___3        : 1;    /*!< Pin 3 Output Enable (0: Disable, 1: Enable)  */
            uint32_t CR___4        : 1;    /*!< Pin 4 Output Enable (0: Disable, 1: Enable)  */
            uint32_t CR___5        : 1;    /*!< Pin 5 Output Enable (0: Disable, 1: Enable)  */
            uint32_t CR___6        : 1;    /*!< Pin 6 Output Enable (0: Disable, 1: Enable)  */
            uint32_t CR___7        : 1;    /*!< Pin 7 Output Enable (0: Disable, 1: Enable)  */
            uint32_t CR___8        : 1;    /*!< Pin 8 Output Enable (0: Disable, 1: Enable)  */
            uint32_t CR___9        : 1;    /*!< Pin 9 Output Enable (0: Disable, 1: Enable)  */
            uint32_t CR___10       : 1;    /*!< Pin 10 Output Enable (0: Disable, 1: Enable) */
            uint32_t CR___11       : 1;    /*!< Pin 11 Output Enable (0: Disable, 1: Enable) */
            uint32_t CR___12       : 1;    /*!< Pin 12 Output Enable (0: Disable, 1: Enable) */
            uint32_t CR___13       : 1;    /*!< Pin 13 Output Enable (0: Disable, 1: Enable) */
            uint32_t CR___14       : 1;    /*!< Pin 14 Output Enable (0: Disable, 1: Enable) */
            uint32_t CR___15       : 1;    /*!< Pin 15 Output Enable (0: Disable, 1: Enable) */
            uint32_t RESERVED      : 16;   /*!< Reserved Bits                                */
        } CR___register;
    };

    // 묘콘셍닸포1：됴8多신릿痰朞嶝（첼多신3貫）
    union {
        volatile uint32_t FR1;               /*!< Port Function Register 1                     */
        struct FR1__Register {            
			uint32_t FR1__0        : 1;    /*!< Pin 0 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR1__1        : 1;    /*!< Pin 1 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR1__2        : 1;    /*!< Pin 2 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR1__3        : 1;    /*!< Pin 3 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR1__4        : 1;    /*!< Pin 4 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR1__5        : 1;    /*!< Pin 5 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR1__6        : 1;    /*!< Pin 6 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR1__7        : 1;    /*!< Pin 7 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR1__8        : 1;    /*!< Pin 8 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR1__9        : 1;    /*!< Pin 9 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR1__10       : 1;    /*!< Pin 10 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR1__11       : 1;    /*!< Pin 11 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR1__12       : 1;    /*!< Pin 12 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR1__13       : 1;    /*!< Pin 13 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR1__14       : 1;    /*!< Pin 14 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR1__15       : 1;    /*!< Pin 15 Function Enable (0: Disable, 1: Enable) */
            uint32_t RESERVED      : 16;   /*!< Reserved Bits                                */
        } FR1__register;
    };

    // 묘콘셍닸포2：멕8多신릿痰朞嶝（첼多신3貫）
    union {
        volatile uint32_t FR2;               /*!< Port Function Register 2                     */
        struct FR2__Register {
			uint32_t FR2__0        : 1;    /*!< Pin 0 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR2__1        : 1;    /*!< Pin 1 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR2__2        : 1;    /*!< Pin 2 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR2__3        : 1;    /*!< Pin 3 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR2__4        : 1;    /*!< Pin 4 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR2__5        : 1;    /*!< Pin 5 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR2__6        : 1;    /*!< Pin 6 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR2__7        : 1;    /*!< Pin 7 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR2__8        : 1;    /*!< Pin 8 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR2__9        : 1;    /*!< Pin 9 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR2__10       : 1;    /*!< Pin 10 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR2__11       : 1;    /*!< Pin 11 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR2__12       : 1;    /*!< Pin 12 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR2__13       : 1;    /*!< Pin 13 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR2__14       : 1;    /*!< Pin 14 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR2__15       : 1;    /*!< Pin 15 Function Enable (0: Disable, 1: Enable) */
            uint32_t RESERVED      : 16;   /*!< Reserved Bits                                */
        } FR2__register;
    };

    // 묘콘셍닸포3：윈嵐묘콘토零（첼多신3貫）
    union {
        volatile uint32_t FR3;               /*!< Port Function Register 3                     */
        struct FR3__Register {
			uint32_t FR3__0        : 1;    /*!< Pin 0 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR3__1        : 1;    /*!< Pin 1 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR3__2        : 1;    /*!< Pin 2 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR3__3        : 1;    /*!< Pin 3 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR3__4        : 1;    /*!< Pin 4 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR3__5        : 1;    /*!< Pin 5 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR3__6        : 1;    /*!< Pin 6 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR3__7        : 1;    /*!< Pin 7 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR3__8        : 1;    /*!< Pin 8 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR3__9        : 1;    /*!< Pin 9 Function Enable (0: Disable, 1: Enable)  */
            uint32_t FR3__10       : 1;    /*!< Pin 10 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR3__11       : 1;    /*!< Pin 11 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR3__12       : 1;    /*!< Pin 12 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR3__13       : 1;    /*!< Pin 13 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR3__14       : 1;    /*!< Pin 14 Function Enable (0: Disable, 1: Enable) */
            uint32_t FR3__15       : 1;    /*!< Pin 15 Function Enable (0: Disable, 1: Enable) */
            uint32_t RESERVED      : 16;   /*!< Reserved Bits                                */

        } FR3__register;
    };

    uint32_t RESERVED0[5];              /*!< Reserved Registers (5 * 32-bit)              */

    // 역짤왠齡셍닸포：16몸多신데뗌토零
    union {
        volatile uint32_t OD;                /*!< Port Open Drain Control Register             */
        struct OD___Register {
            uint32_t OD___0        : 1;    /*!< Pin 0 Open Drain (0: CMOS, 1: Open Drain)    */
            uint32_t OD___1        : 1;    /*!< Pin 1 Open Drain (0: CMOS, 1: Open Drain)    */
            uint32_t OD___2        : 1;    /*!< Pin 2 Open Drain (0: CMOS, 1: Open Drain)    */
            uint32_t OD___3        : 1;    /*!< Pin 3 Open Drain (0: CMOS, 1: Open Drain)    */
            uint32_t OD___4        : 1;    /*!< Pin 4 Open Drain (0: CMOS, 1: Open Drain)    */
            uint32_t OD___5        : 1;    /*!< Pin 5 Open Drain (0: CMOS, 1: Open Drain)    */
            uint32_t OD___6        : 1;    /*!< Pin 6 Open Drain (0: CMOS, 1: Open Drain)    */
            uint32_t OD___7        : 1;    /*!< Pin 7 Open Drain (0: CMOS, 1: Open Drain)    */
            uint32_t OD___8        : 1;    /*!< Pin 8 Open Drain (0: CMOS, 1: Open Drain)    */
            uint32_t OD___9        : 1;    /*!< Pin 9 Open Drain (0: CMOS, 1: Open Drain)    */
            uint32_t OD___10       : 1;    /*!< Pin 10 Open Drain (0: CMOS, 1: Open Drain)   */
            uint32_t OD___11       : 1;    /*!< Pin 11 Open Drain (0: CMOS, 1: Open Drain)   */
            uint32_t OD___12       : 1;    /*!< Pin 12 Open Drain (0: CMOS, 1: Open Drain)   */
            uint32_t OD___13       : 1;    /*!< Pin 13 Open Drain (0: CMOS, 1: Open Drain)   */
            uint32_t OD___14       : 1;    /*!< Pin 14 Open Drain (0: CMOS, 1: Open Drain)   */
            uint32_t OD___15       : 1;    /*!< Pin 15 Open Drain (0: CMOS, 1: Open Drain)   */
            uint32_t RESERVED      : 16;   /*!< Reserved Bits                                */
        } OD___register;
    };

    // 윗왠齡셍닸포：16몸多신데뗌토零
    union {
        volatile uint32_t PUP;               /*!< Port Pull-up Control Register                */
        struct PUP__Register {
            uint32_t PUP__0       : 1;    /*!< Pin 0 Pull-up (0: Disable, 1: Enable)        */
            uint32_t PUP__1       : 1;    /*!< Pin 1 Pull-up (0: Disable, 1: Enable)        */
            uint32_t PUP__2       : 1;    /*!< Pin 2 Pull-up (0: Disable, 1: Enable)        */
            uint32_t PUP__3       : 1;    /*!< Pin 3 Pull-up (0: Disable, 1: Enable)        */
            uint32_t PUP__4       : 1;    /*!< Pin 4 Pull-up (0: Disable, 1: Enable)        */
            uint32_t PUP__5       : 1;    /*!< Pin 5 Pull-up (0: Disable, 1: Enable)        */
            uint32_t PUP__6       : 1;    /*!< Pin 6 Pull-up (0: Disable, 1: Enable)        */
            uint32_t PUP__7       : 1;    /*!< Pin 7 Pull-up (0: Disable, 1: Enable)        */
            uint32_t PUP__8       : 1;    /*!< Pin 8 Pull-up (0: Disable, 1: Enable)        */
            uint32_t PUP__9       : 1;    /*!< Pin 9 Pull-up (0: Disable, 1: Enable)        */
            uint32_t PUP__10      : 1;    /*!< Pin 10 Pull-up (0: Disable, 1: Enable)       */
            uint32_t PUP__11      : 1;    /*!< Pin 11 Pull-up (0: Disable, 1: Enable)       */
            uint32_t PUP__12      : 1;    /*!< Pin 12 Pull-up (0: Disable, 1: Enable)       */
            uint32_t PUP__13      : 1;    /*!< Pin 13 Pull-up (0: Disable, 1: Enable)       */
            uint32_t PUP__14      : 1;    /*!< Pin 14 Pull-up (0: Disable, 1: Enable)       */
            uint32_t PUP__15      : 1;    /*!< Pin 15 Pull-up (0: Disable, 1: Enable)       */
            uint32_t RESERVED     : 16;   /*!< Reserved Bits                                */
        } PUP__register;
    };

    // 苟윗왠齡셍닸포：16몸多신데뗌토零
    union {
        volatile uint32_t PDN;               /*!< Port Pull-down Control Register              */
        struct PDN__Register {
            uint32_t PDN__0       : 1;    /*!< Pin 0 Pull-down (0: Disable, 1: Enable)      */
            uint32_t PDN__1       : 1;    /*!< Pin 1 Pull-down (0: Disable, 1: Enable)      */
            uint32_t PDN__2       : 1;    /*!< Pin 2 Pull-down (0: Disable, 1: Enable)      */
            uint32_t PDN__3       : 1;    /*!< Pin 3 Pull-down (0: Disable, 1: Enable)      */
            uint32_t PDN__4       : 1;    /*!< Pin 4 Pull-down (0: Disable, 1: Enable)      */
            uint32_t PDN__5       : 1;    /*!< Pin 5 Pull-down (0: Disable, 1: Enable)      */
            uint32_t PDN__6       : 1;    /*!< Pin 6 Pull-down (0: Disable, 1: Enable)      */
            uint32_t PDN__7       : 1;    /*!< Pin 7 Pull-down (0: Disable, 1: Enable)      */
            uint32_t PDN__8       : 1;    /*!< Pin 8 Pull-down (0: Disable, 1: Enable)      */
            uint32_t PDN__9       : 1;    /*!< Pin 9 Pull-down (0: Disable, 1: Enable)      */
            uint32_t PDN__10      : 1;    /*!< Pin 10 Pull-down (0: Disable, 1: Enable)     */
            uint32_t PDN__11      : 1;    /*!< Pin 11 Pull-down (0: Disable, 1: Enable)     */
            uint32_t PDN__12      : 1;    /*!< Pin 12 Pull-down (0: Disable, 1: Enable)     */
            uint32_t PDN__13      : 1;    /*!< Pin 13 Pull-down (0: Disable, 1: Enable)     */
            uint32_t PDN__14      : 1;    /*!< Pin 14 Pull-down (0: Disable, 1: Enable)     */
            uint32_t PDN__15      : 1;    /*!< Pin 15 Pull-down (0: Disable, 1: Enable)     */
            uint32_t RESERVED     : 16;   /*!< Reserved Bits                                */
        } PDN__register;
    };

    uint32_t RESERVED1;                 /*!< Reserved Register                            */

    // 渴흙왠齡셍닸포：16몸多신데뗌토零
    union {
        volatile uint32_t IE;                /*!< Port Input Control Register                  */
        struct IE___Register {
            uint32_t IE___0        : 1;    /*!< Pin 0 Input Enable (0: Disable, 1: Enable)   */
            uint32_t IE___1        : 1;    /*!< Pin 1 Input Enable (0: Disable, 1: Enable)   */
            uint32_t IE___2        : 1;    /*!< Pin 2 Input Enable (0: Disable, 1: Enable)   */
            uint32_t IE___3        : 1;    /*!< Pin 3 Input Enable (0: Disable, 1: Enable)   */
            uint32_t IE___4        : 1;    /*!< Pin 4 Input Enable (0: Disable, 1: Enable)   */
            uint32_t IE___5        : 1;    /*!< Pin 5 Input Enable (0: Disable, 1: Enable)   */
            uint32_t IE___6        : 1;    /*!< Pin 6 Input Enable (0: Disable, 1: Enable)   */
            uint32_t IE___7        : 1;    /*!< Pin 7 Input Enable (0: Disable, 1: Enable)   */
            uint32_t IE___8        : 1;    /*!< Pin 8 Input Enable (0: Disable, 1: Enable)   */
            uint32_t IE___9        : 1;    /*!< Pin 9 Input Enable (0: Disable, 1: Enable)   */
            uint32_t IE___10       : 1;    /*!< Pin 10 Input Enable (0: Disable, 1: Enable)  */
            uint32_t IE___11       : 1;    /*!< Pin 11 Input Enable (0: Disable, 1: Enable)  */
            uint32_t IE___12       : 1;    /*!< Pin 12 Input Enable (0: Disable, 1: Enable)  */
            uint32_t IE___13       : 1;    /*!< Pin 13 Input Enable (0: Disable, 1: Enable)  */
            uint32_t IE___14       : 1;    /*!< Pin 14 Input Enable (0: Disable, 1: Enable)  */
            uint32_t IE___15       : 1;    /*!< Pin 15 Input Enable (0: Disable, 1: Enable)  */
            uint32_t RESERVED      : 16;   /*!< Reserved Bits                                */
        } IE___register;
    };
} WROS_PORT__TypeDef;


typedef struct {
    // TBxEN (Enable register)
    union {
        volatile uint32_t EN;                /*!< TB Enable Register                           */
        struct EN___Register {
            uint32_t RESERVED1	: 6;   /*!< Reserved Bits (Read as 0)                    */
            uint32_t TB_HALT		: 1;    /*!< Clock operation during debug HALT (0: Run, 1: Stop) */
            uint32_t TB___EN		: 1;    /*!< TMRBx operation (0: Disable, 1: Enable)      */              
        } EN___register;
    };

    // TBxRUN (RUN register)
    union {
        volatile uint32_t RUN;               /*!< TB RUN Register                              */
        struct RUN__Register {
            uint32_t TB__RUN		: 1;    /*!< Count operation (0: Stop & clear, 1: Count)  */
            uint32_t RESERVED3	: 1;    /*!< Reserved Bit (Read as 0)                     */
            uint32_t TB_PRUN		: 1;    /*!< Prescaler operation (0: Stop & clear, 1: Count) */               
        } RUN__register;
    };

    // TBxCR (Control register)
    union {
        volatile uint32_t CR;                /*!< TB Control Register                          */
        struct TBCR_Register {
            uint32_t C__SSEL		: 1;    /*!< Counter Start select (0: Software start, 1: External trigger) */
            uint32_t TRG_SEL		: 1;    /*!< External Trigger select (0: Rising edge, 1: Falling edge) */
            uint32_t RESERVED5	: 1;    /*!< Write as 0                                   */
            uint32_t I__2_TB		: 1;    /*!< Operation at IDLE mode (0: Stop, 1: Operation) */
            uint32_t RESERVED6    : 1;    /*!< Read as 0                                    */
            uint32_t TB_SYNC		: 1;    /*!< Synchronous mode switch (0: individual, 1: synchronous) */
            uint32_t RESERVED7    : 1;    /*!< Write as 0                                   */
            uint32_t TB__WBF      : 1;    /*!< Double buffer (0: Disable, 1: Enable)        */
        } TBCR_register;
    };

    // TBxMOD (Mode register)
    union {
        volatile uint32_t MOD;               /*!< TB Mode Register                             */
        struct MOD__Register {
            uint32_t TB__CLK		: 3;    /*!< Selects the TMRBx source clock               */
            uint32_t TB__CLE		: 1;    /*!< Up-counter control (0: Disable clearing, 1: Enables clearing) */
            uint32_t TB__CPM		: 2;    /*!< Capture timing                               */
            uint32_t TB___CP		: 1;    /*!< Capture by softwareTB (0: Capture, 1: Don't care) */
            uint32_t TB_RSWR 		: 1;    /*!< Write to timer registers 0 and 1 (0: No, 1: Yes) */
        } MOD__register;
    };

    // TBxFFCR (Flip-flop control register)
    union {
        volatile uint32_t FFCR;              /*!< TB Flip-Flop Control Register                */
        struct FFCR_Register {
            uint32_t TB_FF0C       : 2;    /*!< TBxFFD control                               */
            uint32_t TB_E0T1       : 1;    /*!< TBxFFD reverse trigger (TBxRG0 match) (0: Disable, 1: Enable) */
            uint32_t TB_E1T1       : 1;    /*!< TBxFFD reverse trigger (TBxRG1 match) (0: Disable, 1: Enable) */
            uint32_t TB_C0T1       : 1;    /*!< TBxFFD reverse trigger (TBxCP1 capture) (0: Disable, 1: Enable) */
            uint32_t TB_C1T1       : 1;    /*!< TBxFFD reverse trigger (TBxCP0 capture) (0: Disable, 1: Enable) */
        } FFCR_register;
    };

    // TBxST (Status register)
    union {
        volatile  uint32_t ST;                /*!< TB Status Register                           */
        struct ST___Register {
            uint32_t INTTB0       : 1;    /*!< Match flag (TBxRG0) (0: No match, 1: Match)  */
            uint32_t INTTB1       : 1;    /*!< Match flag (TBxRG1) (0: No match, 1: Match)  */
            uint32_t INTTBOF      : 1;    /*!< Overflow flag (0: No overflow, 1: Overflow)  */
        } ST___register;
    };

    // TBxIM (Interrupt mask register)
    union {
        volatile uint32_t IM;                /*!< TB Interrupt Mask Register                   */
        struct IM___Register {
            uint32_t TB__IM0		: 1;    /*!< Match interrupt mask (TBxRG0) (0: Disable, 1: Enable) */
            uint32_t TB__IM1		: 1;    /*!< Match interrupt mask (TBxRG1) (0: Disable, 1: Enable) */
            uint32_t TB_IMOF		: 1;    /*!< Overflow interrupt mask (0: Disable, 1: Enable) */
        } IM___register;
    };

    // TBxUC (Up counter capture register)
    union {
        volatile  uint32_t UC;                /*!< TB Up-counter Capture Register               */
        struct UC___Register {
            uint32_t TBUC         : 16;   /*!< Captured up-counter value                    */
            uint32_t RESERVED18   : 16;   /*!< Reserved Bits (Read as 0)                    */
        } UC___register;
    };

    // TBxRG0 (Timer register 0)
    union {
        volatile uint32_t RG0;               /*!< TB RG0 Timer Register                        */
        struct RG0__Register {
            uint32_t TB__RG0        : 16;   /*!< Value compared to the up-counter             */
            uint32_t RESERVED20   : 16;   /*!< Reserved Bits (Read as 0)                    */
        } RG0__register;
    };

    // TBxRG1 (Timer register 1)
    union {
        volatile uint32_t RG1;               /*!< TB RG1 Timer Register                        */
        struct RG1__Register {
            uint32_t TB__RG1        : 16;   /*!< Value compared to the up-counter             */
            uint32_t RESERVED22   : 16;   /*!< Reserved Bits (Read as 0)                    */
        } RG1__register;
    };

    // TBxCP0 (Capture register 0)
    union {
        volatile  uint32_t CP0;               /*!< TB CP0 Capture Register                      */
        struct CP0__Register {
            uint32_t TB__CP0		: 16;   /*!< Captured up-counter value                    */
            uint32_t RESERVED24	: 16;   /*!< Reserved Bits (Read as 0)                    */
        } CP0__register;
    };

    // TBxCP1 (Capture register 1)
    union {
        volatile  uint32_t CP1;               /*!< TB CP1 Capture Register                      */
        struct CP1__Register {
            uint32_t TB__CP1		: 16;   /*!< Captured up-counter value                    */
            uint32_t RESERVED26	: 16;   /*!< Reserved Bits (Read as 0)                    */
        } CP1__register;
    };
} WROS_TIMER_TypeDef;

typedef struct
{
    // EN (Enable Register)
    union
    {
        uint32_t EN;
        struct EN_Register
        {
            uint32_t SIOE			: 1;  /* 눔왯繫돛꾸鱗：0=쐐痰，1=賈콘 */
            uint32_t BRCKSEL		: 1;  /* 渡롸틉포渴흙珂爐朞嶝：0=┵T0/2，1=┵T0 */
            uint32_t Reserved_0	: 30; /* 貫2-31，괏즛（怜뗍槨0） */
        } EN_register;
    };
	
    // BUF (Buffer Register)
    union
    {
        uint32_t BUF;
        struct BUF_Register
        {
            uint32_t DATA_Buffer	: 8;  /* 澗랙뻠녑鑒앴，畇槨랙箇뻠녑，뗍槨쌈澗뻠녑 */
            uint32_t Reserved_0	: 24; /* 괏즛貫 */
        } BUF_register;
    };

    // CR (Control Register)
    union
    {
        uint32_t CR;
        struct CR_Register
        {
            uint32_t IOC			: 1;  /* 珂爐渴흙/渴놔친駕朞嶝：0=渴놔，1=渴흙 */
            uint32_t SCLKS		: 1;  /* 珂爐懶朞嶝：0=RXD苟슉懶랙、懶澗；1=SCLK懶랙、苟슉懶澗 */
            uint32_t FERR			: 1;  /* 煉댄轎깃羚：0=攣끽，1=댄轎（뗍珂헌쥐） */
            uint32_t PERR			: 1;  /* 펜탉/퓐潼댄轎깃羚：0=攣끽，1=댄轎（뗍珂헌쥐） */
            uint32_t OERR			: 1;  /* 淚놔댄轎깃羚：0=攣끽，1=댄轎（뗍珂헌쥐） */
            uint32_t PEN			: 1;  /* 펜탉叫駱賈콘：0=쐐痰，1=賈콘 */
            uint32_t EVEN			: 1;  /* 펜탉叫駱잚謹：0=펜，1=탉 */
            uint32_t RB8			: 1;  /* 쌈澗鑒앴貫8（쏭9貫UART친駕） */
            uint32_t TIDLE		: 2;  /* 離빈寧貫渴놔빈돨TXD榴檄：00=됴，01=멕，10=괏넣離빈寧貫 */
            uint32_t TXDEMP		: 1;  /* 퓐潼댄轎珂돨TXD榴檄：0=됴，1=멕 */
            uint32_t Reserved_0	: 1; /* 괏즛貫 */
            uint32_t EHOLD		: 3;  /* 離빈寧貫괏넣珂쇌：000=2/fsys 逞 110=128/fsys */
            uint32_t Reserved_1	: 1; /* 괏즛貫 */
            uint32_t Reserved_2	: 16; /* 괏즛貫 */
        } CR_register;
    };

    // MOD0 (Mode Control Register 0)
    union
    {
        uint32_t MOD0;
        struct MOD0_Register
        {
            uint32_t SC			: 2;  /* 눔왯눈渴珂爐朞嶝：00=TMRB渴놔，01=꺼景쪽랙포，10=溝固珂爐，11=棍꼬珂爐 */
            uint32_t SM			: 2;  /* 눈渴친駕：00=I/O쌈왯，01=7貫UART，10=8貫UART，11=9貫UART */
            uint32_t WU			: 1;  /* 뻥今묘콘賈콘：0=쐐痰，1=賈콘（쏭9貫UART친駕） */
            uint32_t RXE			: 1;  /* 쌈澗賈콘：0=쐐痰，1=賈콘 */
            uint32_t CTSE			: 1;  /* CTS壞癎묘콘賈콘：0=쐐痰，1=賈콘 */
            uint32_t TBit8		: 1;  /* 눈渴鑒앴貫8（쏭9貫UART친駕） */
            uint32_t Reserved_2	: 24; /* 괏즛貫 */
        } MOD0_register;
    };

    // BRCR (Baud Rate Generator Control Register)
    union
    {
        uint32_t BRCR;
        struct BRCR_Register
        {
            uint32_t BRS			: 4;  /* 롸틉궐N：0000=N=16 逞 1111=N=15 */
            uint32_t BRCK			: 2;  /* 꺼景쪽랙포渴흙珂爐朞嶝：00=┵TS0 된 */
            uint32_t BRADDE		: 1;  /* N + (16-K)/16 롸틉묘콘賈콘：0=쐐痰，1=賈콘 */
            uint32_t Reserved_5	: 1;  /* 괏즛貫 */
            uint32_t Reserved_6	: 24; /* 괏즛貫 */
        } BRCR_register;
    };

    // BRADD (Baud Rate Generator Control Register 2)
    union
    {
        uint32_t BRADD;
        struct BRADD_Register
        {
            uint32_t BRK			: 4;  /* K令：0001=K=1 逞 1111=K=15（K=0쐐岺） */
            uint32_t Reserved_7	: 28; /* 괏즛貫 */
        } BRADD_register;
    };

    // MOD1 (Mode Control Register 1)
    union
    {
        uint32_t MOD1;
        struct MOD1_Register
        {
            uint32_t EMPTY		: 1; /* 괏즛貫 */
            uint32_t SINT			: 3;  /* 젯崎눈渴쇌몰珂쇌：000=轟 逞 111=64≠SCLK鷺퍅 */
            uint32_t TXE			: 1;  /* 눈渴賈콘：0=쐐痰，1=賈콘 */
            uint32_t FDPX			: 2;  /* 눈渴친駕零：00=쐐岺，01=곕崗묏澗，10=곕崗묏랙，11=홍崗묏 */
            uint32_t I2SC			: 1;  /* IDLE친駕꾸鱗：0=界岺，1=頓契 */
            uint32_t Reserved_3	: 24; /* 괏즛貫 */
        } MOD1_register;
    };

    // MOD2 (Mode Control Register 2)
    union
    {
        uint32_t MOD2;
        struct MOD2_Register
        {
            uint32_t SWRST		: 2;  /* 흡숭릿貫：01∪10 뇰랙릿貫 */
            uint32_t WBUF			: 1;  /* 崗뻠녑賈콘：0=쐐痰，1=賈콘 */
            uint32_t DRCHG		: 1;  /* 눈渴렘蕨：0=LSB膽邱，1=MSB膽邱 */
            uint32_t SBLEN		: 1;  /* 界岺貫낀똑：0=1貫，1=2貫 */
            uint32_t TXRUN		: 1;  /* 눈渴櫓깃羚：0=界岺，1=頓契 */
            uint32_t RBFLL		: 1;  /* 쌈澗뻠녑찮깃羚：0=왕，1=찮 */
            uint32_t TBEMP		: 1;  /* 눈渴뻠녑왕깃羚：0=찮，1=왕 */
            uint32_t Reserved_4	: 24; /* 괏즛貫 */
        } MOD2_register;
    };

    // RFC (Receive FIFO Configuration Register)
    union
    {
        uint32_t RFC;
        struct RFC_Register
        {
            uint32_t RIL			: 2;  /* 쌈澗櫓뙤FIFO輕념섬깎：00-11뚤壇꼇谿곕崗묏/홍崗묏토零 */
            uint32_t Reserved_11	: 4;  /* 貫2-5，괏즛 */
            uint32_t RFIS			: 1;  /* 쌈澗櫓뙤냥係숭：0=된黨RIL，1=댕黨된黨RIL */
            uint32_t RFCS			: 1;  /* 쌈澗FIFO헌뇜：0=꼇밑懃，1=헌뇜 */
            uint32_t Reserved_12	: 24; /* 貫8-31，괏즛 */
        } RFC_register;
    };

    // TFC (Transmit FIFO Configuration Register)
    union
    {
        uint32_t TFC;
        struct TFC_Register
        {
            uint32_t TIL			: 2;  /* 랙箇櫓뙤FIFO輕념섬깎：00-11뚤壇꼇谿곕崗묏/홍崗묏토零 */
            uint32_t Reserved_13	: 4;  /* 貫2-5，괏즛 */
            uint32_t TFIS			: 1;  /* 랙箇櫓뙤냥係숭：0=된黨TIL，1=鬼黨된黨TIL */
            uint32_t TFCS			: 1;  /* 랙箇FIFO헌뇜：0=꼇밑懃，1=헌뇜 */
            uint32_t TBCLR		: 1;  /* 랙箇뻠녑헌뇜：0=꼇밑懃，1=헌뇜 */
            uint32_t Reserved_14	: 23; /* 貫9-31，괏즛 */
        } TFC_register;
    };

    // RST (Receive FIFO Status Register)
    union
    {
        uint32_t RST;
        struct RST_Register
        {
            uint32_t RLVL			: 3;  /* 쌈澗FIFO輕념榴檄：000=왕 돕 100=4俚쌘 */
            uint32_t Reserved_15	: 4;  /* 貫3-6，괏즛 */
            uint32_t ROR			: 1;  /* 쌈澗FIFO淚놔：0=灌냥，1=냥 */
            uint32_t Reserved_16	: 24; /* 貫8-31，괏즛 */
        } RST_register;
    };

    // TST (Transmit FIFO Status Register)
    union
    {
        uint32_t TST;
        struct TST_Register
        {
            uint32_t TLVL			: 3;  /* 랙箇FIFO섬깎榴檄：000=왕 돕 100=4俚쌘 */
            uint32_t Reserved_17	: 4;  /* 貫3-6，괏즛 */
            uint32_t TUR			: 1;  /* 랙箇FIFO퓐潼：0=灌냥，1=냥 */
            uint32_t Reserved_18	: 24; /* 貫8-31，괏즛 */
        } TST_register;
    };

    // FCNF (FIFO Configuration Register)
    union
    {
        uint32_t FCNF;
        struct FCNF_Register
        {
            uint32_t CNFG			: 1;  /* FIFO賈콘：0=쐐痰，1=賈콘 */
            uint32_t RXTXCNT		: 1;  /* 菱땡쐐痰RXE/TXE：0=轟，1=菱땡쐐痰 */
            uint32_t RFIE			: 1;  /* 쌈澗FIFO櫓뙤賈콘：0=쐐痰，1=賈콘 */
            uint32_t TFIE			: 1;  /* 랙箇FIFO櫓뙤賈콘：0=쐐痰，1=賈콘 */
            uint32_t RFST			: 1;  /* 쌈澗FIFO賈痰俚쌘鑒：0=離댕，1=宅쌈澗FIFO輕념섬깎宮谿 */
            uint32_t Reserved_9	: 3;  /* 貫5-7，극伎畇000 */
            uint32_t Reserved_10	: 24; /* 貫8-31，괏즛 */
        } FCNF_register;
    };

} WROS_UART__TypeDef;

#elif defined(A34M418)

#else
	#error "MCU Undefine"
#endif

/* =========================================================================================================================== */
/* ================                                           SPI0                                            ================ */
/* =========================================================================================================================== */

/* =========================================================================================================================== */
/* ================                                           I2C0                                            ================ */
/* =========================================================================================================================== */

/* =========================================================================================================================== */
/* ================                                            CAN                                            ================ */
/* =========================================================================================================================== */

/* =========================================================================================================================== */
/* ================                                           MPWM0                                           ================ */
/* =========================================================================================================================== */

/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */


#define WROS_PERI_BASE			(0x40000000UL)
#define BITBAND_WROS_PERI_BASE	(0x42000000UL)

#define WROS_CORE_M4_BASE		(0xE0000000UL)


#define WROS_CORTEX_M4				(WROS_CORE_M4_BASE	+ 0x000E000UL)

#if defined(TMPM470)
// 셍닸포샘뒈囹
#define WROS_CLOCK__BASE			(WROS_PERI_BASE	+ 0x00F3000UL)

#define WROS_PA_____BASE			(WROS_PERI_BASE	+ 0x00C0000UL)
#define WROS_PB_____BASE			(WROS_PERI_BASE	+ 0x00C0100UL)
#define WROS_PC_____BASE			(WROS_PERI_BASE	+ 0x00C0200UL)
#define WROS_PD_____BASE			(WROS_PERI_BASE	+ 0x00C0300UL)
#define WROS_PE_____BASE			(WROS_PERI_BASE	+ 0x00C0400UL)
#define WROS_PF_____BASE			(WROS_PERI_BASE	+ 0x00C0500UL)
#define WROS_PG_____BASE			(WROS_PERI_BASE	+ 0x00C0600UL)
#define WROS_PH_____BASE			(WROS_PERI_BASE	+ 0x00C0700UL)
#define WROS_PJ_____BASE			(WROS_PERI_BASE	+ 0x00C0800UL)
#define WROS_PK_____BASE			(WROS_PERI_BASE	+ 0x00C0900UL)
#define WROS_PL_____BASE			(WROS_PERI_BASE	+ 0x00C0A00UL)
#define WROS_PN_____BASE			(WROS_PERI_BASE	+ 0x00C0C00UL)
#define WROS_PP_____BASE			(WROS_PERI_BASE	+ 0x00C0D00UL)

#define WROS_TIMER0_BASE			(WROS_PERI_BASE  + 0x00C4000UL)
#define WROS_TIMER1_BASE			(WROS_PERI_BASE  + 0x00C4100UL)
#define WROS_TIMER2_BASE			(WROS_PERI_BASE  + 0x00C4200UL)
#define WROS_TIMER3_BASE			(WROS_PERI_BASE  + 0x00C4300UL)
#define WROS_TIMER4_BASE			(WROS_PERI_BASE  + 0x00C4400UL)
#define WROS_TIMER5_BASE			(WROS_PERI_BASE  + 0x00C4500UL)
#define WROS_TIMER6_BASE			(WROS_PERI_BASE  + 0x00C4600UL)
#define WROS_TIMER7_BASE			(WROS_PERI_BASE  + 0x00C4700UL)
#define WROS_TIMER8_BASE			(WROS_PERI_BASE  + 0x00C4800UL)
#define WROS_TIMER9_BASE			(WROS_PERI_BASE  + 0x00C4900UL)

#define WROS_UART0_BASE				(WROS_PERI_BASE  + 0x00E1000UL)
#define WROS_UART1_BASE				(WROS_PERI_BASE  + 0x00E1100UL)
#define WROS_UART2_BASE				(WROS_PERI_BASE  + 0x00E1200UL)
#define WROS_UART3_BASE				(WROS_PERI_BASE  + 0x00E1300UL)

#define WROS_WDT___BASE				(WROS_PERI_BASE  + 0x00F2000UL)

#define WROS_FLASH_BASE				(WROS_PERI_BASE  + 0x1DFF0000UL)

#elif defined(TMPM380)
// 셍닸포샘뒈囹
#define WROS_CLOCK__BASE			(WROS_PERI_BASE	+ 0x0040200UL)

#define WROS_PA_____BASE			(WROS_PERI_BASE	+ 0x0000000UL)
#define WROS_PB_____BASE			(WROS_PERI_BASE	+ 0x0000040UL)
#define WROS_PC_____BASE			(WROS_PERI_BASE	+ 0x0000080UL)
#define WROS_PD_____BASE			(WROS_PERI_BASE	+ 0x00000C0UL)
#define WROS_PE_____BASE			(WROS_PERI_BASE	+ 0x0000100UL)
#define WROS_PF_____BASE			(WROS_PERI_BASE	+ 0x0000140UL)
#define WROS_PG_____BASE			(WROS_PERI_BASE	+ 0x0000180UL)
#define WROS_PH_____BASE			(WROS_PERI_BASE	+ 0x00001C0UL)
#define WROS_PI_____BASE			(WROS_PERI_BASE + 0x0000200UL)
#define WROS_PJ_____BASE			(WROS_PERI_BASE	+ 0x0000240UL)
#define WROS_PK_____BASE			(NULL)
#define WROS_PL_____BASE			(WROS_PERI_BASE	+ 0x00002C0UL)
#define WROS_PM_____BASE			(WROS_PERI_BASE + 0x0000300UL)
#define WROS_PN_____BASE			(WROS_PERI_BASE	+ 0x0000340UL)
#define WROS_PP_____BASE			(WROS_PERI_BASE	+ 0x0000380UL)

#define WROS_TIMER0_BASE			(WROS_PERI_BASE + 0x0010000UL)
#define WROS_TIMER1_BASE			(WROS_PERI_BASE + 0x0010040UL)
#define WROS_TIMER2_BASE			(WROS_PERI_BASE + 0x0010080UL)
#define WROS_TIMER3_BASE			(WROS_PERI_BASE + 0x00100C0UL)
#define WROS_TIMER4_BASE			(WROS_PERI_BASE + 0x0010100UL)
#define WROS_TIMER5_BASE			(WROS_PERI_BASE + 0x0010140UL)
#define WROS_TIMER6_BASE			(WROS_PERI_BASE + 0x0010180UL)
#define WROS_TIMER7_BASE			(WROS_PERI_BASE + 0x00101C0UL)
#define WROS_TIMER8_BASE			(NULL)
#define WROS_TIMER9_BASE			(NULL)

#define WROS_UART0_BASE				(WROS_PERI_BASE + 0x0020080UL)
#define WROS_UART1_BASE				(WROS_PERI_BASE + 0x00200C0UL)
#define WROS_UART2_BASE				(WROS_PERI_BASE + 0x0020100UL)
#define WROS_UART3_BASE				(WROS_PERI_BASE + 0x0020140UL)
#define WROS_UART4_BASE				(WROS_PERI_BASE + 0x0020180UL)

#define WROS_WDT___BASE				(WROS_PERI_BASE + 0x0040000UL)

#define WROS_FLASH_BASE				(WROS_PERI_BASE + 0x1FFF010UL)

#elif defined(A34M418)
// 셍닸포샘뒈囹
#define WROS_CLOCK__BASE			(WROS_PERI_BASE	+ 0x0000000UL)

#define WROS_PA_____BASE			(WROS_PERI_BASE	+ 0x0000000UL)
#define WROS_PB_____BASE			(WROS_PERI_BASE	+ 0x0001100UL)
#define WROS_PC_____BASE			(WROS_PERI_BASE	+ 0x0001200UL)
#define WROS_PD_____BASE			(WROS_PERI_BASE	+ 0x0001300UL)
#define WROS_PE_____BASE			(WROS_PERI_BASE	+ 0x0001400UL)
#define WROS_PF_____BASE			(WROS_PERI_BASE	+ 0x0001500UL)
#define WROS_PG_____BASE			(WROS_PERI_BASE	+ 0x0001600UL)

#define WROS_TIMER0_BASE			(WROS_PERI_BASE + 0x0003000UL)
#define WROS_TIMER1_BASE			(WROS_PERI_BASE + 0x0003040UL)
#define WROS_TIMER2_BASE			(WROS_PERI_BASE + 0x0003080UL)
#define WROS_TIMER3_BASE			(WROS_PERI_BASE + 0x00030C0UL)
#define WROS_TIMER4_BASE			(WROS_PERI_BASE + 0x0003100UL)
#define WROS_TIMER5_BASE			(WROS_PERI_BASE + 0x0003140UL)
#define WROS_TIMER6_BASE			(WROS_PERI_BASE + 0x0003180UL)
#define WROS_TIMER7_BASE			(WROS_PERI_BASE + 0x00031C0UL)
#define WROS_TIMER8_BASE			(WROS_PERI_BASE + 0x0003200UL)
#define WROS_TIMER9_BASE			(WROS_PERI_BASE + 0x0003240UL)

#define WROS_UART0_BASE				(WROS_PERI_BASE + 0x0008000UL)
#define WROS_UART1_BASE				(WROS_PERI_BASE + 0x0008100UL)
#define WROS_UART2_BASE				(WROS_PERI_BASE + 0x0008200UL)
#define WROS_UART3_BASE				(WROS_PERI_BASE + 0x0008300UL)
#define WROS_UART4_BASE				(WROS_PERI_BASE + 0x0008400UL)
#define WROS_UART5_BASE				(WROS_PERI_BASE + 0x0008500UL)

#define WROS_WDT___BASE				(WROS_PERI_BASE + 0x0000200UL)

#define WROS_FLASH_BASE				(WROS_PERI_BASE + 0x1000000UL)

#else
	#error "MCU Undefine"
#endif

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */



/** @} */ /* End of group Device_Peripheral_declaration */
extern		WROS_CORE_M4_Typedef*	WROS_CORE_M4;

extern		WROS_CLKGE_TypeDef*		WROS_CLK_GE;

extern		WROS_PORT__TypeDef*		WROS_____PA;
extern		WROS_PORT__TypeDef*		WROS_____PB;
extern		WROS_PORT__TypeDef*		WROS_____PC;
extern		WROS_PORT__TypeDef*		WROS_____PD;
extern		WROS_PORT__TypeDef*		WROS_____PE;
extern		WROS_PORT__TypeDef*		WROS_____PF;
extern 		WROS_PORT__TypeDef*		WROS_____PG;
extern 		WROS_PORT__TypeDef*		WROS_____PH;
extern 		WROS_PORT__TypeDef*		WROS_____PJ;
extern 		WROS_PORT__TypeDef*		WROS_____PK;
extern 		WROS_PORT__TypeDef*		WROS_____PL;
extern 		WROS_PORT__TypeDef*		WROS_____PN;
extern		WROS_PORT__TypeDef*		WROS_____PP;

extern		WROS_TIMER_TypeDef*		WROS_TIER_0;
extern		WROS_TIMER_TypeDef*		WROS_TIER_1;
extern		WROS_TIMER_TypeDef*		WROS_TIER_2;
extern		WROS_TIMER_TypeDef*		WROS_TIER_3;
extern		WROS_TIMER_TypeDef*		WROS_TIER_4;
extern		WROS_TIMER_TypeDef*		WROS_TIER_5;

extern		WROS_UART__TypeDef*		WROS_UART_0;
extern		WROS_UART__TypeDef*		WROS_UART_1;
extern		WROS_UART__TypeDef*		WROS_UART_2;
extern		WROS_UART__TypeDef*		WROS_UART_3;

extern		WROS_WDT___TypeDef*		WROS_WDT__0;

enum{ Pin__In,	Pin_Out };



#define WROS_BITBAND_PERI(addr, bitnum)	(BITBAND_WROS_PERI_BASE + (((uint32_t)(addr) & 0x00FFFFFF) << 5) + ((uint32_t)(bitnum) << 2))

#define GPIO_DATA(PinID, Num)			(*((volatile uint32_t *)WROS_BITBAND_PERI(&((WROS_____P ## PinID)->DATA),Num)))

void WROS_Init(void);

/************************************************************************
************************************************************************
                                ARM_CORTEX
************************************************************************
************************************************************************/
#define __ASM	__asm

void __enable_interrupt(void);
void __disable_interrupt(void);


void __DSB(unsigned int unused);
void __ISB(unsigned int unused);


/************************************************************************
************************************************************************
                                Driver_Struct
************************************************************************
************************************************************************/
//        TIMER
void WROS_Base_Timer(void);
void WROS_Tick_Init(void);
void WROS_TimerTask(T_DispInfo*);
void WROS_NVIC_Init(void);
void WROS_NVIC_Setting(UINT8,UINT8,UINT8);

typedef enum{ SPI,				IIC																													}T_Device_Type;
typedef enum{ Initial_Dev_0,	Device_Index_1,		Device_Index_2,		Device_Index_3,	Device_Index_4,	Device_Index_5,	Device_Index_6				}T_Device_Step;
typedef enum{ Serial_Oneshot,	Serial_Keep,		Serial_Busy,		Serial_Sleep																}T_Comm_State;
typedef enum{ Serial_Start,		Serial_Write_mode,	Serial_Read_mode,	Serial_TX_Adr,	Serial_RX_Adr,	Serial_TX_DATA,	Serial_RX_DATA,	Serial_Stop	}T_Comm_Step;
typedef enum{ NONE,				Echo_ACK,			Echo_NCK,			Write_ACK,		Read_ACK														}T_Echo_Step;

typedef void(*Device_NextStep)();
typedef T_Echo_Step(*Device_Event)(volatile UINT32*, volatile UINT32*, volatile UINT32*);
typedef struct
{
	T_Device_Type Device_Type;
	T_Device_Step Device_Step;
	T_Comm_State Comm_Request;
	T_Comm_Step Comm_Step;

	struct
	{
		UINT8 Adr_Size;
		UINT8 Adr_Index;
		UINT8 Adr[4];

		UINT16 Data_Size;
		UINT16 Data_Index;
		UINT8 Data[320];
	}T_Serial_Packet;

	volatile UINT32* Eable_Pin;
	volatile UINT32* Clock_Pin;
	volatile UINT32* ChipS_Pin;
	volatile UINT32* DataW_Pin;
	volatile UINT32* Write_Pin_state;        //
	volatile UINT32* DataR_Pin;
	volatile UINT32* Read_Pin_state;

	void (*Device_NextStep)(void);

	T_Echo_Step EchoReq;
	T_Echo_Step (*Device_Event)(volatile UINT32*, volatile UINT32*, volatile UINT32*, volatile UINT32*, volatile UINT32*);
}T_Serial_Interface_drive;

extern T_Serial_Interface_drive        LCD_Device;
extern T_Serial_Interface_drive        Flash_Device;
extern T_Serial_Interface_drive        Mpu6050_Device;

#ifndef SET
#define SET		1
#endif

#ifndef CLEAR
#define CLEAR	0
#endif


#endif /* WROS_H */

